1. Field of the Invention
The present invention relates to a method of forming a pattern for a semiconductor device, and more specifically, to a method of forming a pattern from stacked films.
2. Description of the Background Art
A method of forming an interconnection pattern for a conventional semiconductor device will be described below.
FIGS. 19 to 21 are schematic cross sectional views showing, in order, the steps involved in the method of forming an interconnection pattern for a conventional semiconductor device. In FIG. 19, a first conductive film 101 and a second conductive film 102 are stacked in this order on an insulating film 103. A resist pattern 104 is formed on a prescribed region of second conductive film 102 by a common photolithographic technique.
Insulating film 103 is formed, for example, of silicon oxide (SiO.sub.2), first conductive film 101 is formed of titanium (Ti) or titanium nitride (TiN), and second conductive film 102 is formed of aluminum (Al). Moreover, first conductive film 101 is formed as barrier metal to suppress the chemical reaction between insulating film 103 and second conductive film 102, and second conductive film 102 is formed as a main electrical conduction layer.
An example of the thickness for the films is 100 nm for first conductive film 101, 100 nm for second conductive film 102, and 500 nm for resist pattern 104.
Then, second conductive film 102 and first conductive film 101 are etched in this order using resist pattern 104 as a mask.
As seen in FIG. 20, as a result of etching, second conductive film 102 and first conductive film 101 are patterned in this order, while resist pattern 104 remains on second conductive film 102.
One example of etching conditions for these films 101 and 102 when an ICP (Inductively Coupled Plasma)-type etching device is used is as follows:
Etching gas and its flow rate: Cl.sub.2 /BCl.sub.3 /CF.sub.4 =80/20/20 sccm (sccm representing a volumetric flow (cm.sup.3 /min) in a normal state);
Normal pressure: 15 mTorr; PA1 Source power: 700 W; and PA1 Bias power: 60 W.
With these conditions, the etch selectivity of first conductive film 101 or second conductive film 102 to resist pattern 104 (etched amount of first conductive film 101 or second conductive film 102/etched amount of resist pattern 104) is approximately 0.5 to approximately 0.8. Therefore, with the above conditions, a thickness of at least about 500 nm is required for resist 104.
Thereafter, resist pattern 104 is removed, an upper surface of second conductive film 102 is exposed as seen in FIG. 21, and the patterning of interconnection is complete.
As higher degrees of integration is achieved in semiconductor devices, the width and spacing of interconnection is becoming smaller. An accurate transfer of a resist pattern is necessary for the formation of such minute interconnection. As the pattern gets smaller, however, the interconnection width also is reduced in size so that the aspect ratio of the resist pattern becomes greater. Thus, in FIG. 19, as interconnection width Wr and interconnection spacing Wo become smaller due to miniaturization, the aspect ratio given by thickness Tr of resist pattern 104/width Wr (or Wo) becomes larger. Thus, as resist pattern 104 becomes long and narrow, resist pattern 104 may fall to the side, and as the spacing between resist pattern 104 gets narrower, the pattern may stick together.
In order to prevent such problems from occurring, either of the two following approaches must be employed: either the aspect ratio of resist pattern 104 must be reduced, or etching of interconnection must be performed using a hard mask. The method of using a hard mask involves etching the hard mask formed on an interconnection layer using a resist pattern as a mask, and after removing the resist pattern by ashing, patterning the interconnection using the patterned hard mask as a mask.
The former approach, however, in view of the reduced interconnection width and spacing due to the higher degree of integration of semiconductor devices, cannot be used with the conventional method of forming an interconnection pattern. The latter approach, on the other hand, has the problem of a great increase in the number of steps involved in processing the hard mask.